1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and, more particularly, to a gate array of a silicon-on-insulator (SOI) construction.
2. Description of Related Art
A gate array is frequently employed as one of ICs devoted to particular applications. The gate array has a construction comprised of a matrix array of basic logical gates on a semiconductor chip, and is marketed after metallization adapted to the user's requests.
The gate array construction is roughly divided into two types, one being a channel construction having a gate region and a channel region for metallization in the gate region, and the other being a channel-less construction having transistors laid on its entire surface without vacancies, sometimes referred to as a sea-of-gates (SOG).
FIGS. 12 and 13 show a part (an nMOS section) of a typical conventional gate array. In FIG. 12, a layer patterned to a substantially U-shape on a well (substrate) is a gate electrode 102 of an nMOS transistor, source drain regions 103, 103 of which are formed on both sides of a narrow strip-like region 102a interconnecting both enlarged end sections functioning as wiring or metallization. Each basic unit cell is constituted by a pair of the gate electrodes 102, 102 having the enlarged end sections extending in alternately opposite directions. Each basic unit cell is surrounded by a device isolating region (LOCOS region) 105 when seen in a plan view. A region 104 defined between two adjoining basic unit cells is used for contacting with a (substrate). FIG. 13 is a cross-section taken along line XIII--XIII in FIG. 12. A p-type well region 106 is formed on an n-type silicon substrate 101. The source drain regions 103 are n.sup.+ type impurity diffusion regions in the p-type well region 106, whilst the region 104 is a p.sup.+ type impurity diffusion region.
In consideration of the demand for high integration and higher layout efficiency, the recent tendency is to use the channel-less gate array in preference to the channel gate array. As far as circuit performance is concerned, an analog hybrid type has also become known, which is adapted for dealing not only with digital signals but also with analog signals, as reported for example in NIKKEI ELECTRONICS, No. 484, page 122 to 123, published by NIKKEI BP KK.
Meanwhile, although the gate scale is increased markedly with the channel-less gate array, a problem is presented that, when the hybrid system channel-less gate array is to be implemented, the gate scale is diminished. That is, although capacitance or resistance devices may be built in a metallization area in a channel type gate array, there is no region dedicated to metallization in the channel-less gate array, so that how to array capacitive or resistance devices for analog components raises a problem. If the capacitive or resistance devices are forcedly formed on a chip, the number of the logic gates is diminished in an amount corresponding to an area taken up by these devices, thus obstructing the increase of the gate scale.